Embodiments of the disclosure relate to a system on chip (SoC), and more particularly, to a SoC for packetizing a symbol including multiple bytes using indicator data indicating a PHY protocol interface (PPI) packetizing method and a data processing system including the same.
As the resolution of a display increases, a display controller transmitting data to the display needs to increase the transmission speed of the data. A display interface standard, mobile industry processor interface (MIPI) display serial interface (DSI), includes a DSI host controller and a D-PHY. When the frequency of a clock signal used between the DSI host controller and the D-PHY increases, power consumption of the DSI also increases.
Timing closure is getting more difficult during DSI manufacturing. Timing closure is a process of modifying a field-programmable gate array (FPGA) or very large-scale integration (VSLI) design to satisfy FPGA or VLSI timing requirements. Most of modifications are processed by electronic design automation (EDA) tools according to instructions given by a designer.
When a host controller of a DSI transmits image data byte by byte to a D-PHY, the D-PHY serializes the image data and transmits the serialized image data to a display driver integrated circuit (IC). When the frequency of a clock signal of the D-PHY of the DSI is increased to process high-resolution image data as the resolution of a display increases, timing closure becomes difficult and the power consumption of the DSI increases.